Cadence hosts emulation on “datacentre-class” installations

November 17, 2015 // By Graham Prophet
Cadence says it, “Ushers in [a] new era of datacenter-class emulation” with its Palladium Z1 Enterprise Emulation Platform. Claims include up to 5x greater emulation throughput, with an average 2.5x greater workload efficiency than competitors; and scalability from IP blocks to full Systems-on-Chip with capacity of up to 9.2 billion gates.

With enterprise-level reliability and scalability, the Palladium Z1 platform executes up to 2304 parallel jobs and scales up to 9.2 billion gates, addressing the growing market requirement for emulation technology that can be efficiently utilized across global design teams to verify increasingly complex systems-on-chip (SoCs).

And early user comment has been solicited from Nvidia; “The design and verification of our very complex devices requires us to employ sophisticated tools such as hardware emulation for fast and reliable system development,” said Narenda Konda, director of engineering at NVIDIA. “Due to the Palladium Z1 platform's capacity to handle our billion gate-class designs and its highly sophisticated debug and advanced multiuser capabilities, all in a small form factor, we will be able to design and deliver our next generation GPU and Tegra designs with high quality and on schedule.” [video at; / www.cadence.com/news/PalladiumZ1/Nvidia]

Calling it, “a true datacentre resource enabling maximum utilisation,” Cadence builds the platform on a rack-based blade architecture to provide 92% smaller footprint and 8X better gate density than the [prior] Palladium XP II platform. Palladium Z1 offers a unique virtual target relocation capability, and payload allocation into available resources at run time, avoiding re-compiles. With its massively parallel processor-based architecture, Palladium Z1 platform claims 4X better user granularity than its nearest competitor.

“For our advanced SoC designs we are facing thousands of verification payloads of varying sizes from dozens of different projects,” said Daniel Diao, deputy general manager of the Turing Processor Business Unit at Huawei. “The Palladium Z1 platform uniquely met our requirements due to its reliability as a datacenter compute resource, offering advanced multi-user capabilities and scalability from small four million gate verification payloads to multi-billion gate designs, allowing us to ensure system functionality in short project schedules.”

Features include:

• Less than one-third the power consumption per emulation cycle of the Palladium XP II platform. This is enabled by an up to 44% reduction in power