Cadence moves to a more software-centric approach to complex SoC verification

December 12, 2014 // By Graham Prophet
Cadence’s Perspec System Verifier claims up to ten-times productivity improvement in system-on-chip verification by, among other strategies, automating some of the manual tasks when preparing system-level coverage-driven test development. It marks a shift towards software-driven verification, rather than (or, as well as) one that starts at the hardware logic level.

Perspec focuses on use-case scenarios; that is, a top-down rather than bottom-up approach to system verification in which the test are derived from the final, intended, functionality of the device. Part of what Perspec does centres on examining the range of possible tests that can be derived from the high-level functionality, and selecting those that give a high level of test coverage.

Perspec produces tests that can be used and re-used at a number of different stages of a complex system's development, specifically at each level of abstraction at which the chip is depicted, prior to silicon implementation.

Claims for Perspec include that it reduces complex use-case scenario development effort for SoC verification from weeks to days; and that it improves SoC quality by accelerating the development of complex software-driven tests and integrated debug to reproduce, find and fix complex SoC-level bugs.

Perspec’s use-case scenario-based software-driven system-on-chip (SoC) verification is driven by a graphical specification of system-level verification scenarios and a definition of the SoC topology and actions; it can reduce complex test development from weeks to days, Cadence says, while also allowing design teams to reproduce, find and fix complex bugs to improve overall SoC quality.