Additionally, a new signal-integrity flow introduces a higher level of automation that gives usability and productivity benefits for circuit simulation of performance-driven digital circuits requiring pre-layout topology and constraint exploration and development for high-speed design.
OrCAD 16.6 PSpice improves user productivity by providing simulation convergence improvements and an average 20 percent gain in simulation speed. The significant performance gains are achieved through the introduction of multi-core support for simulations involving large designs and designs dominated by complex models such as MOSFETs and BJTs.
The expanded/new signal-integrity flow in release 16.6 provides a seamless, bidirectional interface between the OrCAD Capture and the OrCAD PCB SI products. This new integration enables an automated and comprehensive design methodology that streamlines pre-layout topology and constraint exploration improving productivity by 100 percent.
OrCAD 16.6 also extends the Tcl programming capability and apps methodology from OrCAD Capture to PSpice. As a result, users can extend and customize their simulations and environment beyond what is possible with a standard ‘out-of-box’ solution. With Tcl access to the simulation data and environment, users may customize simulations with tolerances on any parameter, map user parameters, or program PSpice with user-defined equations and expressions.
The Cadence OrCAD 16.6 PCB technology is scheduled to be available in Q4 2012.
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