Forte is a long-established provider of SystemC-based high-level synthesis (HLS) and arithmetic IP: Cadence’s Charlie Huang, senior vice president of the System & Verification Group says that, “Growth in the high-level synthesis market segment is accelerating... HLS tools are now addressing a broader application space and producing equal or better quality of results than hand-coded RTL, fuelling worldwide adoption and production deployment amongst leading companies.”
Forte’s tools are relevant to datapath-centric designs, arithmetic IP, SystemC IP and IP development tools. Forte’s Cynthesizer HLS product features strong support for memory scheduling, especially for highly parallel or pipelined designs. Cadence says that this complements the high QoR (quality-of-results) for transaction-level modelling, under-the-hood RTL synthesis and incremental ECO support featured by Cadence’s own C-to-Silicon Compiler.
Sean Dart, CEO of Forte anticipates a, “combination [that] will benefit customers through a standardised system-level flow, improved product capabilities for both customer bases, and integration all the way to silicon.”