Cadence Signoff Solution shaves weeks from design cycle and timing convergence for complex STMicroelectronics SoC

October 10, 2012 // By Paul Buckley
STMicroelectronics has slashed multiple weeks from its design schedule on a 28-nm system-on-chip (SoC) by switching to the Cadence signoff solution.

In concert with the Cadence RTL-to-GDSII flow, ST deployed Cadence signoff technologies to gain better quality of results and productivity while accelerating time to market in the tapeout of an advanced SoC.

“The Cadence signoff solution cut weeks off our development schedule,” said Thierry Bauchon, R&D director for STMicroelectronics’ Unified Platform Division. “In one 24-hour period, for instance, we were able to fix thousands of hold violations across more than 60 mode-corner combinations on this design, which contained more than 20 million cells - something that would have taken us weeks to close with our prior signoff technology.”

ST achieved its time-to-tapeout benefits by leveraging the integration of Cadence Encounter Timing System with Cadence QRC Extraction in conjunction with Encounter Digital Implementation (EDI) System.

At 28-nm and below, increased variation due to smaller drawn devices increases the amount of process corners required for signoff to ensure working silicon. Encounter Timing System uniquely delivers comprehensive physically aware, multi-mode, multi-corner (MMMC) analysis across the design flow, engineering change orders (ECOs), and final signoff. ST cited the ability to understand the placement of cells during timing optimization, along with the ability to distribute many modes and corners for analysis, as key to improving the quality of the ECOs and the turnaround time of final design closure.

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