Cadence tool yields faster power analysis for SoC design

August 05, 2015 // By Graham Prophet
Cadence’s Joules RTL Power tool claims 20-times faster time-based power analysis to within 15% accuracy to signoff; the software works with Cadence’s Palladium emulation platform for early system-level power analysis and optimisation

This register-transfer level (RTL) power analysis solution enables system-on-chip (SoC) design teams to analyse power consumption more accurately during design exploration. Built on a multi-threaded architecture, the Joules RTL Power Solution delivers 20x faster time-based RTL power analysis when compared to other methods.

“We see a significant opportunity to improve the capacity and accuracy of power analysis during system-level design exploration,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital and Signoff Group at Cadence. “The Joules RTL Power Solution combines... our production implementation flow with parallel stimulation file processing to offer a power analysis solution that is fast enough for system-level analysis, yet correlates well to signoff results.”

Incorporating rapid prototype technology from the Cadence Genus Synthesis Solution engine, the Joules RTL Power Solution can analyse designs of up to 20 million instances overnight with gate-level accuracy within 15% of final power as signed off in the Cadence Voltus IC Power Integrity Solution. The Joules RTL Power Solution also integrates with Cadence’s Stratus High-Level Synthesis (HLS) platform for early system-level power analysis and optimisation.

Features include:

• Accurate RTL power estimation—The Joules RTL Power Solution performs an ultra-fast design synthesis using a new integrated prototype mode of the Genus Synthesis Solution, including physically aware clock tree and datapath buffering, and enabling accurate RTL power estimation.

• Multi-threaded frame-based architecture—Power analysis is parallelised across multiple CPUs accelerating in-depth power exploration. Multiple stimulus files can be analysed simultaneously and each stimulus file can be time-sliced into frames to enable time-based power reporting.

• Adjustable power analysis resolution—User-selectable frames can be used to zoom in on power-critical periods of the simulation, and multiple stimuli for different design hierarchies can be merged to mimic full SoC traffic and power consumption. This enables design teams to easily analyse critical power problems.

• Advanced data mining and debug—Power can be reported at the bit level or register level and may be