Cadence unveils Virtuoso Advanced Node for 20-nm design

January 28, 2013 // By Paul Buckley
Cadence Design Systems, Inc. has introduced Virtuoso Advanced Node, a new set of breakthrough custom/analog capabilities designed specifically for the advanced technology nodes of 20 nm and below.

Built on the Cadence Virtuoso custom/analog technology, Virtuoso Advanced Node features innovative capabilities that prevent errors before they are created rather than detect them late in the design process. Working in concert with Cadence Encounter RTL-to-GDSII flow, QRC Extraction and Physical Verification System, Virtuoso Advanced Node enables the development of complex mixed-signal chips that power today’s leading consumer electronics devices.

The new and advanced Virtuoso technologies address the toughest challenges facing engineers, including layout-dependent effects (LDEs), double patterning, color-aware layout and new routing layers. They integrate seamlessly with the Cadence Integrated Physical Verification System (IPVS) - a foundry-qualified technology for signoff DRC and DPT checking - to conduct on-the-fly checks that reduce layout iterations.

Virtuoso Advanced Node enables engineers to build their physical design and check it as they go, to ensure they are making the right choice at each step, rather than having to wait until the end.  The node delivers novel technology that helps decrease costly design iterations by allowing designers the ability to use partially completed layout as part of the LDE analysis, detecting layout-dependent effects at the earliest moment in the design cycle.  LDEs - such as stress effects, poly and diffusion spacing/length, well proximity effects, and parasitics - are handled with detailed test benches that analyze multiple corners to ensure that the circuit will function as specified.

When the technique is combined with Cadence MODGENs and constraints, IPVS and final hotspot detection and correction with Virtuoso DFM, users can expect up to a 30 percent improvement in their overall verification time.  By methodically building and checking the design, the designer should eliminate massive 'rip ups' and 'reroutes' that can be found at the end if the circuit wasn’t checked along the way.

Double patterning and color-aware layout - Double patterning, a manufacturing requirement at 20 nanometers, splits the design layers into two masks, separating structures that are too close together. But double patterning brings “coloring”