Cadence updates Allegro with PCB documentation revisions

May 21, 2015 // By Graham Prophet
Cadence has revised features of its PCB design platform Allegro to make design cycles shorter and more predictable; a new manufacturing option streamlines handoff to manufacturing and claims to speed PCB documentation process by up to 60%

The Allegro 16.6 portfolio features several new products and technologies. Included in this release is the new Allegro PCB Designer Manufacturing Option, which can shorten the time to create manufacturing documentation by up to 60%, and several key technology updates intended to increase efficiency, control and productivity for designers, while streamlining handoff to manufacturing. Driven by increasing demands to provide a more predictable and shorter design cycle, the Allegro 16.6 portfolio includes more capabilities that accelerate routing and tuning for high-speed interfaces such as DDR3 and DDR4.

The Allegro 16.6 portfolio includes new products to help PCB designers boost efficiency and productivity, while keeping cost of ownership low. These new products include:

• Allegro PCB Designer Manufacturing Option, a toolset that makes it efficient and cost effective for PCB designers to streamline the development of a release-to-manufacturing package for their products. It includes the Design for Manufacturing (DFM) Checker, Documentation Editor and Panel Editor modules.

• Allegro Rules Developer and Checker, which allows users to develop custom fabrication and assembly rules to extend capabilities provided by Allegro PCB Designer and the Manufacturing Option. This tool provides a relational geometric verification language designed specifically for creating rules that are proprietary and custom to an original equipment manufacturer (OEM). The rules can be viewed and executed from the Allegro Constraint Manager, making it a single source for all design rules checks (DRCs) within a PCB.

The Allegro 16.6 technology portfolio update offers multiple capabilities that boost turnaround time by shortening design cycles, accelerating timing closure and providing more editing control. These capabilities include:

• Adding return path vias while routing differential pairs, ensuring a ground current return path for differential pair vias

• Updates to avoid coupling of high-speed signals to the FR-4 fabric weave, making it easier for designers to create off-angle routes based on user-defined parameters, accelerating the PCB layout process significantly

• Adjusting spacing for signals in interfaces such