Can 3D ICs learn from MEMS manufacturing experience?

February 03, 2014 // By Julien Happich
EETimes Europe's Editor reports on a meeting in Grenoble on 3D IC technology; under the motto “Application Ready”, this year’s TSV Summit was very much focused on how to make 3D IC design an attractive proposition not only for very demanding niche applications, but a cost-efficient one for chips in everyday consumer electronics.

Debates on Grenoble’s Minatec campus were all about figuring out ways to slash manufacturing costs in what turns out to be quite a process-intensive approach to miniaturisation.

Stacking multiple dice together or connecting them via an interposer, the so-called more-than-Moore approach to higher performance devices relies heavily on Through Silicon Via (TSV) interconnects. These involves extra material deposition steps for the vias to be etched and filled ( the hot topic of last year’s 3D TSV Summit ), wafer handling and thinning and then exposing the TSVs through selective etching. A final Chemical Mechanical Planarisation (CMP) step will open up the isolated vias and prepare the wafer to receive micro-bumps on top of the TSVs, so that another prepared wafer can be stacked on top of it (full wafer-to-wafer stacking) or alternatively, marrying together only known-good dice.

“The choice between the reconstituted wafer approach (assembled of known-good dice only) and the full wafer-to-wafer approach will very much depend on the final die size and the associated costs of managing yield”, according one participant. Usually, the smaller the die and the higher the yield, the more cost-efficient it becomes to perform full wafer-to-wafer stacking, effectively skipping a few process steps.

All these processes and assembly steps come on top of the normal IC manufacture, hence the cost-benefits are not always clear, especially in the consumer market where users want a thinner tablet year-on-year but are not overly concerned about having “3D IC inside”: they simply want it cheaper, or to get more performance at the same price.

Among the keynote speakers, there were many IC manufacturers and process equipment vendors, all assembled to demonstrate their readiness for the next killer app, or rather, trying to convince device makers that all the industry would benefit from pushing 3D TSV technology straight into the mass market. Yet, the killer app that would really pull 3D TSVs globally was not clearly identified; perhaps integrated