CEVA DSP cores delivered via Synopsys' DesignWare

November 13, 2013 // By Graham Prophet
An HPC Design kit of optimised embedded memories and logic libraries yields 8% performance improvement and 13% leakage power reduction with smaller area, for CEVA-XC DSPs

CEVA and Synopsys have collaborated to develop highly optimised DSP core implementations for wireless communications applications including base stations and handsets. Results are said to be improved by use of Synopsys’ DesignWare HPC Design Kit, a processor optimisation kit that includes more than 125 standard cells and memory instances, and an ultra-high density memory compiler. CEVA achieved an 8% performance improvement (worst-case operating conditions) over previous results, and a maximum performance of 1.3 GHz in a 28-nm process while also achieving area and power targets for base-station applications. The collaboration reduced leakage power by 13% and total power by 10% while also achieving speed targets for handset applications.

The CEVA-XC DSP architecture features a combination of VLIW (Very Long Instruction Word) and Vector engines that enhances typical DSP capabilities with advanced vector processing. The scalable CEVA-XC architecture offers a selection of highly powerful communication processors, with four generations to date (CEVA-XC321, CEVA-XC323, CEVA-XC4210 and CEVA-XC4500) widely licensed by leading vendors with over 20 design wins to date. The CEVA-XC architecture targets a broad range of communication applications and use cases including LTE-Advanced handsets, wireless infrastructure, Wi-Fi stations and access points, cable modem, satellite modem and more.

Synopsys’ DesignWare HPC Design Kit is an add-on to the DesignWare Duet package of embedded memories and logic libraries. The Duet package contains all the physical IP elements needed to implement a complete SoC including standard cells, SRAM compilers, register files, ROMs, datapath libraries and Power Optimisation Kits (POKs), as well as options for overdrive/low voltage process, voltage and temperature corners (PVTs), multi-channel cells and memory built-in self-test (BIST) and repair. The HPC Design Kit adds fast cache memory instances and performance-tuned flip-flops that enable speed improvement for processor cores of up to 10% over the standard Duet package. To minimise dynamic and leakage power as well as die area, the HPC design kit provides area optimised and multi-bit flip-flops as well as an