CEVA teams with ARM on vector floating-point DSP core for wireless infrastructure

October 16, 2013 // By Nick Flaherty
CEVA has worked with ARM to develop a vector floating-point DSP specifically designed for advanced wireless infrastructure solutions.

The CEVA-XC4500 includes a baseband-dedicated instruction set architecture (ISA), IEEE-compliant floating point support on full vector elements delivering up to 40 GFLOPs performance, comprehensive multi-core support, a fully cached architecture and hardware managed coherency. The core uses as little as 100mW for LTE 2x2 Pico-Cell baseband processing.
The core is fully cacheable with an advanced data cache that includes hardware cache coherency via ARM's AMBA 4 ACE, and includes an advanced system interconnect using a mix of ARM AMBA 4 compliant buses and fast interconnect (FIC) buses to other system blocks. It also comes with a set of LTE eNodeB libraries.
“The CEVA-XC4500 DSP is a game-changer for wireless infrastructure applications, combining powerful fixed- and floating-point vector processing together with the industry’s most advanced multi-core feature set in a flexible, scalable platform," said Eran Briman, vice president of marketing at CEVA. "The DSP was designed to enable the creation of infrastructure SoCs that combine a software-based architecture together with optimized hardware accelerators, realizing maximum performance and power efficiency for any wireless infrastructure use case. We collaborated closely with ARM to ensure comprehensive support for their latest industry-standard interconnect and coherency protocols, enabling our mutual customers leverage the inherent advantages of designing ARM + CEVA-XC multi-core SoCs.”
Several important emerging technologies such as heterogeneous cellular networks (HetNet) and cloud RAN (C-RAN) require more powerful, higher performance processing solutions to deliver on their promise. The CEVA-XC4500 DSP runs at up to 1.3GHz on a 28nm process and the vector DSP engine supports Fixed Point and Floating Point (IEEE compliant) ISA on full vectors. This enables software-defined architecture with a mix of optimized hardware engines for DSP offloading and a range of tightly coupled acceleration blocks (TCE – Tightly Coupled Extensions) are available. Automated data traffic management offers fully parallel hardware acceleration management with no DSP intervention while dynamic scheduling enables symmetric system design with runtime task allocation based on system load