Analog Devices has issued an FPGA-based reference design with software and HDL code that helps verify high-speed systems incorporating JESD204B-compatible data converters. Called the JESD204B Xilinx Transceiver Debug Tool, it supports the 312.5-Mbps to 12.5-Gbps JESD204B data converter-to-FPGA serial data interface, Xilinx 7 series FPGAs and Zynq-7000 All Programmable SoCs. It is available at no cost with ADI converters and provides an on-chip, 2-D statistical eyescan that helps designers of radar arrays, software-defined radio and other high-speed systems more quickly verify the signal integrity of JESD204B data converter-to-FPGA designs using gigabit transceivers. The reference design is a download here and a video is here.
ADI’s reference design gathers data directly from the on-chip Rx margin analysis feature in the 7 series IBERT core and manages the data locally inside the FPGA or one of the ARM dual-core Cortex-A9 MPCore processors, displaying the data on an HDMI monitor or over Ethernet to a remote monitoring station. Typically, other scanning tools measure signals off-chip and require costly test and measurement equipment or transfer the data back over JTAG to be viewed on a host/development PC in the lab.
“The Analog Devices JESD204B Xilinx Transceiver Debug Tool provides on-chip eyescanning that augments the test and measurement process by statistically determining signal integrity inside the FPGA,” said Revathi Narayanan, High Speed I/O product manager, Xilinx. “Where other techniques probe the outside of the FPGA package and acquire the signal before it’s been processed by Xilinx’s automatic gain control and equaliser blocks, ADI’s approach yields a more accurate result by utilising the Xilinx transceiver on-chip eyescan feature to allow developers to monitor the signal integrity and design margin on their JESD204B links inside the FPGA.” More from Xilinx; www.xilinx.com/jesd204
Alternative scanning tools, says ADI, typically measure high-speed data links by generating a pseudo-random bit stream (PRBS) that is checked for bit-level correctness in a closed development environment. This approach does not describe how well the