Providing a flexible on-chip CPU debug architecture, MIPS On-Chip Instrumentation (MIPS OCI) hardware is the centrepiece of the environment. MIPS OCI works with the Codescape MIPS software development kit (SDK) and new Codescape SysProbe technology to create a seamless and efficient debug environment for next-generation designs.
Today’s increasingly complex chips present new debug challenges with SoCs containing many CPU cores and clusters, and often multi-threading capabilities. MIPS OCI is designed to enable engineers to quickly access these many-core, many cluster CPU designs through a highly parallel approach, leading to fast chip-bring-up and very efficient software development, integration and debug.
Imagination notes that, “For our customers who are creating complex chip designs, our new debug environment for MIPS dramatically simplifies integration and debugging. And for potential customers who want to try a MIPS CPU in their SoC design alongside another company’s CPU, they can do so with the lowest possible risk and impact on their debug process. We believe this is a significant step in taking MIPS to the next level and breaking into new designs. With this move, we are alleviating any barriers for companies to choose MIPS.”
MIPS OCI represents a new modular approach to debugging MIPS systems that enables customers to employ the specific configuration needed for their design. It allows flexible probing of cores, and the combining of trace into a single flow. Advanced power management features let users power down CPU cores and clusters without any impact on other CPU cores that are still powered on and without breaking the JTAG chain. It enables breakpoint and trace configuration as well as on-chip data collection – and global state access in multi-cluster systems – without halting the core.
MIPS OCI is included in the newest MIPS Warrior CPUs including the entry-level M-Class M6200, 64-bit multi-threaded I-Class I6400, and high-performance 64-bit P-Class P6600 CPUs, and is backward compatible through JTAG to previous generations of MIPS CPUs. With the