Renesas’ announcement is of the development of a dual-port on-chip static random access memory (SRAM) for in-vehicle infotainment system-on-chips (SoCs) in the 16 nanometer (nm) and later generations. The SRAM is optimised for use as video buffer memory in automotive infotainment SoCs to realise the real-time image processing capabilities necessary for future autonomous-driving vehicle technologies. When testing the new SRAM in a state-of-the-art 16 nm process, it achieved both 688-picosecond (psec) high-speed operation under the low-voltage condition of 0.7 V and the high level integration density of 3.6 Mbit/mm².
Recently, Renesas notes, in-vehicle infotainment systems, such as car navigation systems and advanced driver assistance systems (ADAS), have achieved progress in preparation for the autonomous cars of the future. In these systems, real-time image processing technologies are critical for realising autonomous-driving vehicles, and there are limits to improve this real-time processing capability by only increasing the integration density with even finer feature sizes and using higher clock frequencies.
To resolve these limitations, there have been efforts to improve performance further by using algorithms that break up images into smaller section and process those sections in parallel. The dual-ported on-chip SRAM is now desired for use with these algorithms, since it can perform write and read operations at the same time to achieve approximately twice the performance of standard single-ported on-chip SRAM. Compared to the single-ported SRAM, however, this dual-ported SRAM suffers from several problems, including not only requiring more chip area, but also increased power consumption when access speeds are increased, worse lower limit voltage margins, and other issues.
By adopting a dual-ported SRAM memory cell optimised for FinFET devices, Renesas says it has succeeded in resolving these issues. The company has also applied a word line boost type assist circuit technology developed for single-ported SRAM to enable high-speed read and write operations that are stable at lower voltages, and allow power consumption to be suppressed in a small chip area.