Chip stacks take new tacks

January 26, 2016 // By Rick Merritt
Almost imperceptibly the semiconductor industry made a big turn on the road to chip stacks. The 3-D IC marrying memory and logic using through-silicon vias (TSVs) went from being the hot destination to something in the rear view mirror.

The smartphone application processor was supposed to be the vehicle for TSVs, and Qualcomm was going to be one of its drivers. Now Apple is out front with speculation its next A-series SoC will use TSMC’s wafer-level fan-out process in a 10nm chip in the works for the iPhone 7.

Whether the Apple rumor is true or not, Qualcomm confirmed it is no longer interested in 3D chip stacks with TSVs. The approach cost too much and takes too long to manufacture, said Michael Campbell, a vice president of engineering at Qualcomm in a talk at the Industry Strategy Symposium hosted by the SEMI trade group.

Instead, Campbell pointed to an emerging class of system-in-package technologies such as the device in the Apple Watch that merge multiple die and passive components. “It’s a question of cost and time-to-market…TSVs require a two-year-plus design cycle while these micro packages take 6-12 weeks,” he said.

Heat is a chief problem for TSVs, said Babak Sabi, director of assembly and test development technology at Intel in an ISS talk. “No one has true stacking of memory on logic and unless someone comes up with a thermal solution for the logic die I don’t think anyone’s going to use it,” he said.

Through-hole vias are fine for regular, relatively cool memory, but not logic. (Image: Intel)Click here for larger image
Through-hole vias are fine for regular, relatively cool memory, but not logic. (Image: Intel)