Clock tree design for complex internet infrastructure applications

September 18, 2014 // By Graham Prophet
Silicon Labs has an online, web-based utility that performs a parameterised search among the company's clock tree chips, to build the most appropriate configuration for any given high-complexity digital environment such as Internet infrastructure hardware.

You use Clock Tree Expert with the company's clock tree generation chips, that offer any-to-any frequency generation with precise control over frequency and phase, and with very low jitter. Timing component selection and clock tree design are more important than ever, the company says, because timing ICs provide low-jitter timing references for high-speed 10/40/100G data applications and can greatly impact system-level performance. When specifying clock trees for their applications, hardware designers must ensure critical jitter performance parameters are met with sufficient margin with the minimum number of timing components. Choosing the optimal combination of clocks, oscillators, jitter attenuators and buffers can be a daunting and time-consuming task for a given Internet infrastructure application.

Using Silicon Labs' DSPLL and MultiSynth technologies, the web-based Clock Tree Expert tool recommends the optimal combination of highly integrated, low-jitter, frequency-flexible clocks and oscillators required to consolidate timing BOM into the fewest number of components.

Users simply enter the required frequencies, number of clocks and desired signalling format, and the tool generates a recommended clock tree in seconds using the minimum number of timing components. Experienced users can also use the tool's 'Build Your Own' environment to design clock trees to their exact specifications. The Clock Tree Expert then guides the user to find the optimal timing ICs, save and share clock tree designs, generate a BOM list and order samples.

The company's ICs can be delivered factory-programmed or you can configure them yourself; they have what might be termed “TTP” configuration memory – two-timesprogrammable – that is, you can configure them up to twice.

When combined with industry-best lead times of less than two weeks, Silicon Labs? timing tools significantly accelerate time to market.

Clock Tree Expert provides instant access to Silicon Labs' timing customisation tools, which can be used to generate custom crystal oscillator (XO), voltage-controlled oscillator (VCXO), CMEMS oscillator and CMOS/differential clock generator part numbers (

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