Configurable dual PLL clock generator with less than 200 fs phase jitter

October 30, 2012 // By Julien Happich
The SM803xxx family of highly configurable dual PLL clock generators from Micrel is optimized for ultra-low jitter, excellent crosstalk isolation and enhanced power supply noise rejection.

The device achieves less than 200 femto-second (fs) RMS phase jitter with twelve differential or single-end outputs for frequencies up to 850MHz. FLEX2 supports very demanding applications requiring numerous frequencies, high fan-out, and ultra-low jitter on a single IC. This includes 10/40/100 Gigabit Ethernet, SONET/SDH, CPRI/OBSAI, Fibre Channel, SAS/SATA, and high speed clocking for FPGA and SerDes.

Factory configurable thanks to a fuse-based one-time programmable (OTP) memory, FLEX2 delivers a customized, quick turn and high performance clocking solution that shortens prototyping time and end system design cycle. The SM803xxx is currently available in production quantities and sampling to customers.