Renesas Electronics Europe worked with consulting firm ASTC around development of an ASIC for a consumer electronics customer, and was able to provide a full board support package (secure boot, drivers and OS) before the silicon was available. The end-customer reduced time to market for its new imaging solution.
The ASIC is designed to significantly enhance image quality and video analytics performance by incorporating custom hardware accelerators into a standard ARM Cortex-based ASIC. While Renesas was engaged on the hardware development, ASTC used its VLAB Virtual Platform solution, together with existing ARM toolboxes and models, to create and integrate a virtual platform for the ASIC. Due to the pre-silicon availability of the VLAB virtual platform for software development, and its advanced hardware/software debug capabilities, the Linux port only took a few weeks. As a result, ASTC delivered a Linux kernel running on the virtual platform well before the silicon was available.
ASTC used VLAB with the standard ARM Virtual Platform Toolbox to accelerate the development and integration of the virtual platform. The VLAB ARM Toolbox includes the ARM Cortex-A9 ISS models, the ARM PrimeCell Toolbox, and a QuickStart Reference Virtual Platform. The QuickStart Reference Virtual Platform for customisation comprises a pre-integrated platform with sample kernel and test cases, enabling developers to kick-start development by allowing immediate loading and running of software applications.
After assembling the platform for the Renesas device, Renesas took a standard Linux kernel and ported it to this virtual board in just a few weeks, helping the team achieve the goal of having software running long before hardware availability. Renesas also used this platform to develop the boot code – software that will cause a respin of the ASIC if it is wrong – and test that it was sufficiently robust for the application. Renesas engineers also took advantage of VLAB's easy scripting API to validate boot-from-UART over a range of baud rate conditions, and of the