Cortex-M4F-core MCUs for secure communications control

April 21, 2015 // By Graham Prophet
Toshiba has added to its TX04 Range of ARM Cortex-M4F-based microcontrollers with versions that enable enhanced communication security and contain support for standard encryption protocols

TMPM46BF10FG adds a selection of enhanced security features, suited to applications in Internet of Things (IoT) devices, energy management systems, sensor technology and industrial equipment.

Users of secure communications control systems increasingly require mass memory data for firmware generation management, failure analysis and high-precision consecutive data storage. These requirements for high-level security features, such as tamper detection and information concealment, are addressed by the TMPM46BF10FG. The IC also meets the need to reduce the number of parts on system circuit board parts by supporting large capacity memory.

Based around an ARM Cortex-M4F core, with a maximum operating frequency of 120 MHz, the TMPM46BF10FG incorporates 1024 kByte of flash memory and 514 kByte SRAM required for secure communications control, four types of security circuits for network communications. The MCU also integrates an SLC NAND flash memory controller and 4- and 8-bit error correction circuitry (BCH ECC) that supports memory expansion with 1 Gbit to 4 Gbit SLC NAND flash memory chips.

To provide additional levels of safety, the IC includes a 16 channel interrupt input and a clock-independent watchdog timer, which operates separately from the system clock, improving the safety of system functions. In the case of a system clock malfunction, the watchdog timer is still capable of detecting errors.

The TMPM46BF10FG incorporates a true random number generator (TRNG: SP800-90C standard) through the combination of a random entropy seed generation (ESG) circuit and Hash-DRGB created by the secure hash processor (SHA) and software program. This meets the robust standards of security that are required in network communications. The hardware based AES encryption/decryption process meets FIPS180-4 and FIPS197 standards and reduces the load on the CPU, in combination with a random seed generation circuit (ESG), and a multiple-length arithmetic (MLA) used to calculate elliptic curves for asymmetric ciphers.

The TMPM46BF10FG features direct memory access (32 channel), a 12-bit AD converter (8 channel), 16-bit timer (8 channel), SPP (3 channel), SIO/UART (4 channel),