Silicon Labs' latest family of crystal oscillators (XOs) provide ultra-low jitter reference timing for 10G, 40G and 100G cloud computing and networking equipment. Si535 and Si536 XOs use Silicon Labs’ DSPLL technology to provide performance, stability and flexibility for 10/40G data centre core/access switches, storage area networking equipment, security routers, enterprise switches/routers, and Carrier Ethernet switches and routers.
To support the growing demand for cloud computing-based services, data centre equipment is migrating to higher speed serial data transmission, often 10G or faster. In parallel, there is a significant trend to maximise energy efficiency by consolidating switching, storage and computing resources into fewer components. These trends have given rise to processors, Ethernet switch ICs and FPGAs with integrated high-speed serialiser-deserialiser (SerDes) technology that requires low-jitter timing references. Silicon Labs’ Si535/536 oscillators provide the ultra-low jitter and ±20 ppm stability required by state-of-the-art cloud computing and networking infrastructure equipment.
The Si535/536 XOs offer jitter performance of under 200 femtoseconds (fsec) RMS jitter (integrated from 10 kHz to 1 MHz) for common Ethernet and Fibre Channel reference frequencies. The Si535/536 oscillators support LVDS and LVPECL output formats at 2.5V and 3.3V and offer both ±20 ppm and 31.5 ppm total stability, simplifying interfacing to a wide variety of processors, switches, PHYs and FPGAs. When combined with Silicon Labs’ Si533xx differential clock buffers, the Si535/536 XOs provide low-jitter clock generation and distribution for SoCs requiring multiple high-performance reference clocks.
The Si535/536 oscillators use Silicon Labs’ DSPLL technology to provide a low-jitter clock at high-speed differential frequencies. Unlike a traditional XO in which a different crystal is required for each output frequency, the Si535/536 XOs use a common fixed-frequency crystal to provide stability and reliability and use the DSPLL IC to generate any output frequency. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low-jitter clocks in noisy environments typically found in data centre and networking systems.