The PSoC 4100 family, the lowest-cost ARM-based PSoC, brings PSoC flexibility and integration to cost-sensitive, high-volume applications. The PSoC 4200 family features faster processor and ADC sampling speeds and PLD-based enhanced universal digital blocks (UDBs). Cypress has also released its new $25 PSoC 4 Pioneer Development Kit, which extends PSoC programmability to the Arduino marketplace at a price point geared to drive broad accessibility. Cypress also issued Service Pack 1 for its PSoC Creator 2.2 Integrated Design Environment (IDE), which provides full design support for the 4100 and 4200 families. These products can be ordered/downloaded at www.cypress.com/go/PSoC4
The PSoC 4 programmable system-on-chip architecture combines Cypress’s PSoC analogue and digital fabric and CapSense capacitive touch technology with ARM’s power-efficient Cortex-M0 core. This scalable, cost-efficient architecture provides access to dozens of free PSoC Components—“virtual chips” represented by icons in PSoC Creator—all for prices as low as $1. The new PSoC 4 device class will, Cypress believes, challenge proprietary 8-bit and 16-bit microcontrollers, along with other 32-bit devices.
“Our first two PSoC 4 device families were designed for high-volume, low-end, 8-bit-, 16-bit and 32-bit embedded applications,” said John Weil, Senior Director of PSoC Marketing for Cypress’s Programmable Systems Division. “There are an almost limitless number of applications that can benefit from the high flexibility, low power and low cost of these families.”
CY8C41XX devices offer enhanced CapSense capacitive-touch sensing. Combined with integrated, analogue components including operational amplifiers, low-power comparators, and a fast successive-approximation ADC all on a single chip, the PSoC 4100 family addresses the general purpose 8- and 16-bit MCU markets, easing the transition from proprietary MCU platforms to a powerful and flexible ARM-based platform.
With more processing and enhanced digital capabilities, CY8C42XX devices offer power leakage of only 150 nA while retaining SRAM memory, programmable logic, and the ability to wake up from an interrupt. In stop mode, these devices consume only 20 nA while maintaining wake-up capability from an I/O