DCD’s D16950 offers a new spin on a familiar function

June 05, 2014 // By Graham Prophet
Polish IP company DCD, celebrating its 15th year of operation, has released the D16950, which is an IP Core of a UART, functionally compatible to the OX16C950. It allows serial transmission in two modes: UART and FIFO. In the FIFO mode, internal FIFOs are activated, allowing 128 Bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit modes.

DCD's UART IP Core performs a serial-to-parallel conversion on data characters received from a peripheral device or a MODEM. And for those who need more, the D16950 enables also parallel-to-serial conversion on data characters received from the CPU. The processor can read a complete status of the UART at any time during the functional operation. Reported status information includes the type and condition of transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing or break interrupt). - The D16950 includes a programmable baud rate generator, which is capable of dividing the timing reference clock input by divisors of 1 to (216-1) and to produce a n × clock for driving the internal transmitter logic. Provisions are also included to use this n × clock to drive the receiver logic.

The D16950 UART IP Core is equipped with a complete MODEM-control capability and a processor-interrupt system. Interrupts can be programmed in accordance to specific requirements, minimising computing required to handle the communications link. The D16950 core includes all other UART's (16450, 16550, 16650 and 16750) features and additional functions. ICR registers give additional capabilities of UART configuration. The data transmission can be synchronised by an external clock connected to the RI (for receiver and transmitter) or the DSR (only for receiver) pin. The NMR register enables a 9-bit mode transmission, with or without special character. Writing and reading from/to FIFO may be controlled by trigger level registers, with any value set from 1 to 127.

DCD’s IP Core implements an auto flow control feature, which can significantly reduce software overload and increases the system efficiency, by controlling serial data flow through the RTS output and the CTS input signals.

The D16950 is suitable for applications, where the UART core and the microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip. It's also a proprietary solution