Alternative approaches can include focusing on the “controlled impedance” of PCB transmission lines and/or using other trace-impedance values.
Let us examine a layer-stack design and see how the PCB trace width affects layer count (cost) and trace impedance (performance). In Figure 1, routing channels of the same width are shown on a signal layer for three PCB transmission lines: a 100-Ω differential pair, a 50-Ω and 60-Ω single-ended.
Figure 1: Routing channels of the same width are shown on a signal layer for three PCB transmission lines for a 100-Ω differential pair, a 50-Ω and 60-Ω single-ended.
The 100-Ω differential-pair is usually determined prior to the single-ended and should be fitted in the routing channel (between the vias) without discontinuities because they are usually for higher speed digital signals. Once the trace width and spacing of the 100-Ω differential-pair have been designed, the trace width for 50-Ω or 60-Ω single-ended on the same layer is usually determined accordingly. Changing the trace width alone for the single-ended traces will lead to different trace impedance. The trace routing yield per channel is:
- Right: One 100-Ω differential-pair with 4mil trace / 5.5mil space.
- Middle: Two 60-Ω traces for single-ended with 4mil trace / 4mil space.
- Left: One 50-Ω trace for single-ended with 6.5mil trace / 7.4mil space.
Note: This example assumes that the minimum trace width and spacing are 4 mils (0.004 in./ 0.1 mm).
In this case, the engineer needs to make trade-off decisions on using either 50-Ω traces, which use up more PCB space and possibly more layers, or 60-Ω traces which use up less PCB space and possibly fewer PCB layers.
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