This software release improves design flow runtime for SmartFusion2 SoC FPGAs and IGLOO2 FPGAs. The release also offers greater design efficiency with an improved SmartDesign graphical design canvas along with improved text editor, design reporting and constraints editor capabilities. The improved SERDES wizards have new clocking options which allow for increased flexibility in mixing serial data rates. These new design efficiencies reduce design creation complexity for engineers working with SERDES-based FPGA designs.
Added to the latest version of Libero SoC v11.4 software is full design flow support for the Linux open source operating system. The FlashPro Express tool that comes bundled with the software enables device programming and debugging capabilities for the Linux operating system. These capabilities provide additional efficiencies for the system architects and designers by allowing them to stay in the same development environment throughout the entire design flow.
Shakeel Peera, senior director of product line marketing at Microsemi comments, “We ... want to leverage the large and ever increasing corporate Linux operating system installed base and give our customers the ability to run an entire design exclusively through a comprehensive Linux design flow.”
The Libero SoC v11.4 software toolset is now available for download from Microsemi's website; at
As well as up to 35%, there is a 20% reduction in timing analysis runtime; System Builder and SmartDesign Generation is now two times faster; and File import is now two times faster. Programming features interlude FlashPro5 programming hardware and the FlashPro Express programming tool with support for simplified production programming.
SmartFusion2 FPGAs integrate a flash-based FPGA fabric, a 166 MHz ARM Cortex-M3 processor, advanced security processing accelerators, DSP blocks, SRAM, eNVM and communication interfaces all on a single chip; www.microsemi.com/products/fpga-soc/soc-fpga/smartfusion2
Microsemi's IGLOO2 FPGAs provide a LUT-based fabric, 5G transceiver, high speed GPIO, block RAM, high-performance memory subsystem, and DSP blocks in a differentiated, cost and power optimised architecture; www.microsemi.com/products/fpga-soc/fpga/igloo2-fpga