Design software release for Altera's forthcoming, 14 nm Stratix 10 FPGAs/SoCs

August 05, 2014 // By Graham Prophet
Altera's Stratix 10 design software allows prospective users to begin designs ahead of silicon availabilty (expected next year): the software has a feature termed Fast Forward Compilation that allows greater levels of exploration of performance options.

The early access design software is for Stratix 10 FPGAs and SoCs, and Altera positions it as the the first design software targeting 14-nm FPGAs. Engineers can start Stratix 10 FPGA designs and evaluate the 2x core performance gains Altera has promised based on its Stratix 10 HyperFlex architecture and the Intel 14 nm Tri-Gate process on which it will build the parts. The software incorporates an upgrade that Altera terms its Hyper-Aware design flow.

Altera has previously announced the outline of its Stratix 10 and Arria 10 silicon; the former will be built by Intel in Tri-Gate (a.k.a. Fin-FET) technology at 14 nm design rules. Altera recently announced ( here) that it had successfully produced test chips at Intel, and provided outline expected performanc figures for the new series. Altera has not previewed exact release dates for Stratix 10 siliocn, but has hinted at full tape-out towards the end of 2014, and chips in the second half of 2015.

Developed to enable doubled performance in a design, Fast Forward Compilation pinpoints performance bottlenecks and provides detailed, step-by-step performance improvement recommendations that a user can rapidly implement. Users also receive Fmax (maximum operating frequency) estimates of their design that can be achieved by applying the recommendations Fast Forward Compilation provides. With this innovative design flow, Fast Forward Compilation gives customers an opportunity to maximise overall design performance made possible by Stratix 10 FPGAs and achieve rapid timing closure.

Previously, Altera says, in order to achieve high-performance targets, users often needed to execute multiple, time-consuming design iterations, including trying various design optimisations and re-running full FPGA compiles to determine the effectiveness of design changes. With Fast Forward Compilation, users receive detailed guidance for design optimisation and an estimated design Fmax to exploit the HyperFlex architecture. With these insights, it adds, users will be better able to make decisions for where to most effectively invest development time to increase their design's