Designing and verifying embedded applications based on state machines

March 29, 2013 // By Graham Prophet
Version 7.1 of IAR visualSTATE adds an extensive amount of features for state machine-based design and formal verification

IAR Systems has released a new version of its state machine tool suite IAR visualSTATE. The version adds several new features and integrations to simplify development of complex state- or event-driven embedded systems. IAR visualSTATE allows users to build their design from a high level, structure complex applications, step by step add functions in detail, and automatically generate code that is 100% consistent with the design. It also provides advanced formal verification, analysis and validation that can be used to make sure the applications behave as intended.

To simplify the design process, Submachine states and Design stereotypes are introduced. Submachine states are reusable state machine fragments, similar to a subroutine or function in a programming language. Common patterns can be created once and reused across a design or between designs, and the events and actions can be remapped to suit the point of use. Design stereotypes are named templates that specify the visual appearance of states. These new features greatly speed up the design of complex systems.

Several new possibilities for integrations are added. An open StateChartModel API provides everything needed for users to build their own tools that can manipulate models in IAR visualSTATE. This for example includes tools that check adherence to naming conventions and specialised code generators. It is now also possible for external clients to remotely control the state machine simulator and designer through TCP/IP. This interface provides an automated integration with Fujitsu CGI Studio, which is a software development platform for creating 2D and 3D graphical user interfaces.

In addition to creating state machine models and embedded applications, IAR visualSTATE lets users explore them through formal verification to make sure they do not contain design inconsistencies or logical gaps. The formal verification engine has been extended with several new features, including compositional verification. The compositional verification can dramatically increase the verification performance for certain models. It also provides detailed information on where verification complexity might