Designing JESD204B converter systems for low BER, Part 1

December 01, 2014 // By Ian Beavers & Jeffrey Ugalde, Analog Devices
With the adoption of the new high speed serial digital interface link, known as JESD204B, between converters and FPGAs, the error rate within the digital transmission line cannot be ignored as a potential contributor to the overall BER.

Many real world sampling systems, such as test and measurement equipment, cannot tolerate a high rate of analogue to digital (ADC) or digital to analogue (DAC) processing errors. These systems essentially require a converter with a low bit error rate (BER). Historically, the conversion error rate of the core converter alone is what has dominated the overall BER. However, with the adoption of the new high speed serial digital interface link, known as JESD204B, between converters and FPGAs, the error rate within the digital transmission line cannot be ignored as a potential contributor to the overall BER.

As a third generation serial interface standard, JESD204B data rates top out at 12.5 Gbps per lane and can span multiple lanes per link, with the next generation of the specification pushing beyond 12.5 Gbps. The speed and quantity of data that is sent per link requires careful attention to several key design criteria in order to minimise the overall BER and prevent the digital data communication from being the dominant error contributor of the converter system.

There are several active and passive elements to the converter JESD204B link that, when considered proactively, can effectively mitigate the digital serial data path as the main contributor to the overall BER. The dielectric material used within the PCB, the inter-symbol interference (ISI) created by the lane layout and the transmission line impedance are all passive elements of the system design that can impact the BER of the link. Conversely, active on-chip transmitter and receiver channel compensation techniques as well as automatic adaptation elements can also substantially improve the BER. Several robust measurement techniques exist to isolate and measure the BER of just the JESD204B link, outside the converter core.

To understand, improve and reduce any impact of the JESD204B link BER on the converter, we answer some common questions from JESD204B system design engineers. Firstly, how is JESD204B link BER determined in the first place?

Determining BER for JESD204B links

ADCs and DACs for instrumentation systems often need to meet a strict error rate standard. The quality of many instrumentation systems can be determined by the error rate occurrence. While a typical conversion error rate can be sought within a converter's analogue core, the digital data link to the needs to have a better error rate in order to prevent being the dominant contributor. Therefore, not only does the analogue conversion error rate need to be measured, but also the BER of the digital link transmission.

BER in a serial or parallel digital data transmission is the ratio of the number of detected errors at the receiver divided by the total number of bits sampled. BER testing in a digital data stream implements a long pseudo random sequence that is started within a transmitter using a common seed value at both ends of the transmission. The pseudo random pattern should ideally have a long non-repetitive sequence to test as many digital combinations as possible. However, real pseudo random patterns have a repetitive sequence that can change with different seed values. The receiver will also know the seed value of the sequence and have the expectation of an ideal transmission. The BER is precisely calculated by observing the difference in the received data compared to the ideal pattern. Mis-matches in the pseudo random sequence data, based on the seed value, between both ends are counted as bit errors.

Next page; sources of bit-errors...