Differential fan-out buffers support industry's lowest additive jitter combined with best power supply noise rejection performance

December 13, 2012 // By Paul Buckley
Microsemi Corporation has expanded its communications timing portfolio with its first family of clock distribution differential fan-out buffers.

The 28-part family of buffers supports clock rates of up to 750 MHz; two types of outputs, low voltage positive emitter coupled logic (LVPECL) and low voltage differential signaling (LVDS); and multiple fan-out ratios. Internal and external terminations for inputs eliminate the need for external peripheral components. In addition, the ultra-low additive output jitter leaves the majority of the jitter budget to the high speed transceivers. The combination of these features results in lower bill-of-material (BOM) costs.

The new clock buffers devices are synergistic with Microsemi’s broad timing portfolio and, when used together, provide customers improved board performance and complete timing solutions.


Microsemi’s new fan-out buffers are available in production quantities now.

More information about Microsemi’s fan-out buffers at