DRAM chips for embedded designs integrate Error Correcting Code

November 03, 2014 // By Julien Happich
DRAM manufacturer Intelligent Memory has come up with what the company claims is a revolutionary new JEDEC compliant DRAM memory IC that brings server-grade reliability to any application at board-level.

In mission-critical systems, DRAM soft errors are guarded against with some form of error correction coding, otherwise known as ECC, built into the processors that populate the servers.

To store the additional bits required for the parity-information, the processor requires special server memory modules with a wider data-bus having a 72-bits width where 64 bits are for the data, and 8 bits accommodate the parity information. The server processor and memory combination works to correct any errors, seen or unseen, without service interruption.

The majority of industrial electronics use CPUs, FPGAs and controllers that have no ECC capabilities; small form factor devices can be board-space-limited and lack room for the wider bit-widths used in ECC.

With its Integrated Error Correcting (ECC) DRAM components available in DDR1, DDR2, DDR3, and LPDDR, Intelligent Memory presents a solution to make any application as reliable as a server. The drop-in replacement DRAM ICs perform the ECC error correction within the DRAM chip itself, independent of the processor driving the application.

This allows ECC levels of reliability in nearly all applications without extra DRAM chip or processor requirements, and independent of hardware or software changes. Nearly all memory modules can be built with ECC DRAMs in DIMM, SO-DIMM, and other popular form-factors. The results are 64-bit wide 'Non-ECC' modules that benefit from the use of integrated ECC chips to attain a higher reliability than 72-bit server ECC module with each ECC DRAM chip on the module performing its own separate error correction.

Intelligent Memory;  www.intelligentmemory.com