To fulfill modern electronics requirements, Polish IP Core has been designed with a special concern about lowest possible power consumption. It draws just 37 uW/MHz in 0.18u technology. The DRPIC166X offers 1.3 GHz virtual clock frequency in a 0.18u technological process (800 MHz virtual clock frequency in a 0.35u technology). The soft core is software-compatible with the industry standard PIC 16XXX microcontrollers. DCD's IP Core implements an enhanced Harvard architecture (separate instruction and data memories) with independent address and data buses. The same, it’s 4 times faster compared to the standard architecture.
The 14 bit program memory and 8-bit dual port data memory allow instruction fetch and data operations, to occur simultaneously. The advantage is that the instruction fetch and memory transfers can be overlapped, by multi stage pipeline, so that the next instruction can be fetched from program memory, while the current instruction is executed with data from the data memory. Most instructions are executed within one system clock period, except the instructions which directly operate on PC (GOTO, CALL, RETURN) program counter. The pipeline is being cleared and subsequently refilled at additional one clock cycle.
The DRPIC166X is delivered with fully automated testbench, complete set of tests and DoCDTM on-chip hardware debugger, allowing easy package validation at each stage of the SoC design flow.
More information at DRPIC166X: http://www.dcd.pl/ipcore/82/drpic166x/
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