DSP-based SoC offers improved performance in hearing-aid designs

November 01, 2013 // By Graham Prophet
ON Semiconductor's Ezairo 7100 optimises performance, size and power consumption while offering an open-programmable architecture.

Designers working in hearing health need, ON says, a DSP platform that lies between a completely general-purpose architecture, and a completely dedicated approach, that allows open programming. Also, the ideal device needs to support the complete signal chain – including wireless connectivity – in a carefully selected silicon process to balance density and power consumption with low-noise analogue functions. The chip is therefore a mix of open-programmable blocks and customised accelerators specific to the hearing-aid task. Ezairo 7100 integrated circuits and packaged hybrids form the basis of advanced hearing aids and hearing implant devices. With five times the processing power of previous systems, the system-on-chip (SoC) provides built-in flexibility to support evolving algorithm, wireless and system-level needs. Design challenges that ON had to overcome included, the company says, attention to power supplies and grounding issues so as to maintain audio quality.

Two separate wireless accesses must be supported; NFC is good for ear-to-ear communications across the body (needed by advanced hearing aid designs) but has very short range; RF channles give good range but may not propagate through the body well.

The Ezairo 7100 ICs are highly-integrated and power efficient single chip solutions, with a quad-core architecture that is constructed with a 24-bit open-programmable CFX DSP core. One of the cores is an ARM Cortex-M3 processor that carries out functions such as support for wireless protocols and complements the DSP core – which is a 24-bit, dual-MAC design – with special error-correction and audio coding. The system also (as the thrid and fourth cores) has a “HEAR” configurable accelerator engine, dedicated for audio processing tasks, and a Filter Engine which implements efficient time-domain filters. When combined with non-volatile memory and wireless transceivers, it forms a complete hardware platform.


ON adds that major signal processing capabilities are hardwired in logic blocks while the programmable DSP enables additional signal processing capabilities to be implemented in software, the open architecture being designed