DVCon Europe readies for first presentation, Munich, mid-October

September 30, 2014 // By Graham Prophet
Design and Verification Conference & Exhibition Europe is a conference for the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits.

Sponsored by the Accellera Systems Initiative, DVCon Europe brings chip architects, systems designers, software developers and IP integrators the latest methodologies, techniques, applications and demonstrations on the practical use of EDA and IP languages and standards used in electronic design. Sponsors of the non-profit Accellera Systems Initiative are ARM, Cadence, Mentor Graphics, and Synopsys.

The Technical Program for the conference covers the following themes:

System Level Design

Verification & Validation

IP Reuse and Design Automation

Mixed-Signal Design and Verification

Lower Power Design and Verification

DVCon Europe has selected papers, tutorials and posters around best practices and user experiences on design and verification in SystemC, SystemVerilog, PSL, UVM, UPF, IP-XACT, and more.

Highlights of DVCon Europe, say the organisers, are:

Industry Keynote Speaker: Bernd Adler from Intel Mobile Communications, Germany

14 tutorials moderated by user companies, tool providers and training partners

More than 25 technical paper presentations

Poster session hosting more than 15 posters

Exhibition with demos from training partners, design tool and IP service providers

DVConnect Networking Reception

The conference takes place on Tuesday, October 14 and Wednesday, October 15, 2014 at the City Hilton Hotel, Munich; registration is at; www.dvcon-europe.org/registration