DVCon Europe returns to Munich, November 2015

August 17, 2015 // By Graham Prophet
DVCon – the Design and Verification Conference – is a format successful in the over more than 20 years, that discusses the practical application of leading edge Electronic Design Automation tools and techniques for the design and verification of advanced semiconductors.

The first European running of DVCon took place in Munich 2014, with great success, and the event returns to Munich on 11 th and 12 th November 2015. Sponsored by Accellera Systems Initiative as well as Cadence Design Systems, Synopsys, Mentor Graphics and other leading EDA players, the 2014 event drew in engineers and managers from semiconductor and systems companies across Europe, and provided a forum for original papers and tutorials from the European engineering community.

This year’s event will be larger than the 2014 conference and has, say the organisers, already attracted an exceedingly high submission standard. Areas to be covered include the latest technology advancements, application techniques and domain experience in HDL-based design and verification.

Content planned for DVCon Europe 2015 includes;

24 technical papers , and 16 poster presentations plus panels on the industrial application of specialised design and verification standards, such as SystemC, SystemVerilog, VHDL, UVM or e .

• A keynote speech by a senior industry leader.

15 tutorials focusing on user experiences in system-level design, verification and validation, mixed-signal design and verification, IP reuse and design automation, low power methods, and the increasingly critical topic of functional safety.

• An exhibition featuring the design technologies and tools from top EDA vendors and service providers.

As a media sponsor of the DVCon Europe, EDN Europe will provide further information on the content of the conference as the event approaches, in these newsletters and on www.edn-europe.com – meantime, the Conference site is at; www.dvcon-europe.org