EDA; Equivalence checking tool doubles speed of verifying functional ECOs

June 18, 2013 // By Graham Prophet
Synopsys' Formality Ultra solution reduces effort for each functional engineering change order (ECO) in advanced EDA design flows. It includes advanced matching, visualisation and fast verification technologies, with users reporting 2x speed-up for implementing and verifying functional ECOs

Formality Ultra is a new configuration of the Formality equivalency checking solution. Formality Ultra includes innovative matching and verification technologies to guide designers through the implementation of functional ECOs with minimal impact to the design and verify the correctness of the ECOs in minutes, for multimillion instance designs. These new capabilities will help designers cut in half the time they spend implementing ECOs late in the design cycle and result in shorter, more predictable schedules, the company says.

Complex designs often undergo multiple functional ECOs late in the design process due to changing specifications and functional errors. Each ECO change can adversely impact schedule and predictability of design closure, which causes designers to invest days trying to minimise the impact of every change to the design. This process can add weeks in the late stages of the design cycle.

The new Formality Ultra adds advanced matching techniques that visually highlight the mismatch between the RTL and netlist representations of a design, allowing designers to efficiently zoom in on the changes required to implement an ECO. In addition, a new multi-point verification technology very quickly checks multiple changes made to the design enabling designers to verify the correctness of their ECOs in a matter of minutes on multi-million instance designs.

Synopsys www.synopsys.com