EDA software delivers power integrity analysis for IC designs

August 05, 2014 // By Graham Prophet
Cadence's Voltus-Fi Custom power integrity solution yields foundry-certified SPICE-level accuracy for transistor-level power signoff, with highest EMIR(see below) accuracy, enabled by Spectre Accelerated Parallel Simulator SPICE simulation. The tool produces, the company says, the highest accuracy for advanced node FinFET processes

Voltus-Fi Custom Power Integrity Solution is a transistor-level electromigration and IR-drop (EMIR) solution that delivers foundry-certified SPICE-level accuracy in power signoff to create the fastest path to design closure. It is underpinned by Cadence Spectre Accelerated Parallel Simulator signoff SPICE simulation, providing accuracy at the transistor level to meet complex manufacturing specifications at advanced nodes. It complements Cadence Voltus IC Power Integrity Solution, a full-chip, cell-level power signoff tool, and completes the company's power signoff technology solution.

Voltus-Fi Custom Power Integrity Solution enables designers to shrink the critical power signoff closure and analysis phase through capabilities including:

- Cadence's patented voltage-based iteration method, which requires a smaller memory footprint and runs faster than the industry's traditional current-based iteration method

- Full integration with the Cadence Virtuoso platform, which provides a single design flow that improves designer productivity in analogue and custom block EMIR signoff

- Builds on transistor-level parasitic extraction with Cadence's Quantus QRC Extraction Solution, transistor-level simulation with Cadence Spectre Accelerated Parallel Simulator and Cadence Spectre Extensive Partitioning Simulator and, finally, EMIR results visualisation on real physical layouts for quick analysis, debugging and optimisation

- Integration between Voltus-Fi Custom Power Integrity Solution and Voltus IC Power Integrity Solution, which provides a seamless flow for advanced analogue/ mixed-signal power signoff for designs with mixed transistor-level and cell-level blocks

Cadence; www.cadence.com/news/voltusfi