“Micrium’s µC/OS-III RTOS is [widely use in] safety-critical and risk-averse applications,” said Ian Lankshear, CEO of EnSilica. “Our partnership with Micrium to port µC/OS-III to eSi-RISC, significantly strengthens and further broadens the overall eSi-RISC ecosystem,... reducing time-to-market and the total cost of embedded development.”
Micrium’s µC/OS-III is a pre-emptive and deterministic multi-tasking RTOS with optional round-robin scheduling. It is highly scalable, capable of supporting unlimited application tasks and kernel objects, and also portable, being delivered with complete source code and in-depth documentation. It is resource efficient as the kernel's memory footprint can be scaled down to contain only the features required for the application, typically 6–24 kBytes of code space and 1 kByte of data space. Available extensions provide memory protection, greater application stability, safety, memory and time management, enabling cost-effective certification of complex systems. µC/OS-III is used extensively in safety-critical and risk-averse applications being pre-certified to avionics (DO-178B Level E up to Level A), industrial control (IEC 61508 Safety Integrity Level 1 up to Level 3) and medical (ISO 62304 Class A up to Class C [FDA 510(k)]) standards requirements.
EnSilica’s eSi-RISC is a family of highly configurable and low-power soft processor cores for embedded systems that scale across a wide range of applications and support both 16-bit and 32-bit configurations. The cores have been silicon proven in a variety of ASIC technologies down to 28 nm. The eSi-RISC family includes the eSi-1600 16-bit processor, eSi-3200 32-bit processor, eSi-3250 32-bit processor, eSi-3250sfp incorporating a single precision floating point processor, eSi-3260 32-bit processor with SIMD DSP extensions and eSi-32X0MP 32-bit scalable, asymmetric multicore processor. The processor cores also have configurable memory architecture and configurable cache options.