Enhancements in flexible length instruction extensions (FLIX) for Xtensa LX6 allow for very long instruction word (VLIW) instructions of any length from 4 to 16 Bytes, resulting in code size savings of up to 25% compared to prior Xtensa versions, thus enabling local memory and cache size reductions of up to 25% for the same performance level.
An option for run-time power-down of portions of cache memories yields up to 75% local memory power savings in select operating scenarios with dynamic cache-way control.
More efficient data cache block prefetch lowers system power and boosts system performance by speeding functions such as MemCpy by a factor 6.5, and reducing the total number of system bus read operations by up to 23%.
Reduced dynamic switching power of the processor logic gates saves up to 25%.
“These latest improvements put the Tensilica processors even further ahead of all other processor cores on the market that claim to offer configurability,” said Jack Guedj, corporate vice president of Tensilica products at Cadence. “Only Cadence automates the creation of both hardware and software development tools, allowing customers to create fully optimised processors for many applications in record time and with state-of-the-art software development tools.”
The Xtensa processor generator technology from Cadence blends conventional fixed-architecture processor solutions with the innovation potential of Application Specific Instruction-set Processor (ASIP) tools. Every Xtensa processor includes the common core Xtensa instruction set architecture (ISA) that delivers modern, high-performance RISC processor benefits.
Building on top of this leading-edge control CPU capability, Cadence also delivers dozens of complex DSP options for the Xtensa platform – including the HiFi Audio DSP family and ultra-high-performance imaging and communications DSPs. Licensees of the Xtensa platform can mix and match their choice of preconfigured ISA options, but also have the freedom to innovate new and proprietary instruction set extensions with complete architectural freedom. Unlike other ASIP tools that lack a common core ISA, innovative cores built upon