Cadence Design Systems’ Allegro TimingVision speeds up timing closure by up to 67%. Within Cadence Allegro PCB Designer, the TimingVision environment makes it possible for PCB designers to save significant time in ensuring that signals in an interface meet timing requirements on protocols such as DDR3/DDR4, PCI Express, and SATA.
TimingVision uses an embedded timing engine to analyse the entire interface structure and develop timing goals to help designers visualise real-time delay and phase information directly on a canvas. This greatly reduces manual editing, overall implementation time and designer effort. When combined with the Cadence Sigrity power-aware SI analysis tool, TimingVision environment enables rapid implementation and tuning in compliance with standard interfaces, diminishing trials and errors in fixing timing issues.
TimingVision environment is suitable for any PCBs that include advanced high-speed interfaces; features include:
• Dynamic feedback on the active and related signals during edits on the design canvas
• Auto-interactive Phase Tuning (AiPT), to compensate both static and dynamic phase constraints on a selected set of differential pairs
• Auto-interactive Delay Tuning (AiDT), to compensate for propagation delay, relative propagation delay and total etch length constraints specified in the physical design on a selected set of signals such as a byte lane.
TimingVision environment, along with the auto-interactive routing environment, is available as part of the Allegro PCB High-Speed Option.