Fastest 8051 IP core runs at 29x original 80C51 performance

March 31, 2015 // By Graham Prophet
Polish IP company Digital Core Design’s DQ8051 IP, for FPGA or ASIC implementation, is an extremely-fast implementation of the 8051 MCU core that has a Dhrystone 2.1 performance rating of 0.27292 DMIPS/MHz, which therefore enables a 29.01 times speed-up over the original 80C51 chip operating at the same frequency.

Speed, says DCD, is not everything; the DQ8051’s dynamic power consumption can be as low as 1.2 µW/MHz, which rivals not only all other 8051-compatible cores but also low-power 32-bit processors.

The 8051, DCD comments, although first introduced more than 30 years ago, is believed to be one of the most popular, or even the most popular, microcontroller core in history. Many engineers have a lot of expertise with this CPU and there’s a great amount of legacy code and 8051-based tool chains around. But the 8051 from 1981 with and the DQ8051 from 2015 are very different entities. “Using our fifteen years of experience on the market, we’ve mastered a great portfolio of 8051 IP cores,” says Piotr Kandora, Vice President at Digital Core Design, “if our DT8051 is the World’s smallest 8051, then the DQ8051 is the World’s fastest 8051 for sure. The nearest competition stopped at 26x, with the power consumption almost two times higher than DCD’s.”

DCD’s DQ8051 Dhrystone score rates at 29.01x the original at the same frequency, with the size of 7.5 kgates. The nearest solution consumes almost 12 kgates and achieves no more than 26x speed improvement. The DQ8051 is available with USB, Ethernet, I²C, SPI, UART, CAN, LIN, HDLC, and Smart Card interfaces. The core is also equipped with the company’s DoCD hardware debugger with Instruction Smart Trace technology. IST doesn’t capture addresses of all executed instructions, but only these related to the start of tracing, conditional jumps and interrupts. This method not only saves time but also allows improving the size of the IST buffer and extending the trace history. Captured instructions are read back by DoCD-debug software, analysed and then presented to the user as ASM code and related C lines.

The DQ8051 is delivered with fully automated testbench and complete set of tests, allowing package validation at each stage of SoC design flow. This MCU IP Core is technology independent, and can be used in both ASIC and FPGA technologies.

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