Fastest SPI NOR flash memory targets automotive systems

October 15, 2015 // By Graham Prophet
Macronix’ OctaFlash is presented as a solution for automotive systems in ADAS/cluster/navigation/infotainment/telematics that demand high speed and large data-capacity

Non-volatile memory (NVM) manufacturer Macronix (Hsinchu, Taiwan) claims the fastest SPI NOR flash memory, the OctaFlash MX25UM product family. OctaFlash provides designers with the next generation performance level of x8 I/O serial interface products with an operating frequency of up to 200 MHz and transmission speeds of up to 400 MB/sec, for in-vehicle entertainment, ADAS and camera applications.

OctaFlash is the next-generation series of NOR Flash memory based on the SPI interface and traditional SPI command sets and expands the current I/O from x4 to x8. OctaFlash is backwards compatible with traditional x1 I/O SPI interfaces, allowing users to continue to use the industry standard SPI, thereby minimising design costs, rather than productswhich adopt a completely new interface.

Meeting the ever-increasing demand for vehicle telematics bandwidth, OctaFlash provides the fastest read access operation frequency in the industry, 200 MHz, and supports both DTR (Double Transfer Rate) and STR (Single Transfer Rate) configurations. Compared to the current Quad (x4 I/O) SPI NOR, OctaFlash has twice the I/O and twice the operating frequency, increasing overall efficiency by four times with a maximum transfer rate of 400 MB/sec.

OctaFlash also has comprehensive DTR protocol support. Input and output cycles of all commands, addresses and information support DTR mode, overcoming the inconvenience of traditional SPI which only supports the STR framework for command input and needs to switch between different protocol modes. Similarly, prior SPIs only supported STR mode when performing program or erase operations and only supported DTR mode when reading, while today's OctaFlash supports DTR mode for all three operations, saving the time needed to switch between modes.

The current x1 I/O requires 40 clock cycles for complete SPI access including executing commands, addresses and information, while Quad I/O requires 22 clock cycles. In comparison, the next-generation OctaFlash in DTR operation mode needs only 13 clock cycles, significantly reducing the read latency of SPI products and increasing the efficiency of functions such