Fewer design starts are yielding higher value

March 07, 2012 // By Nicolas Mokhoff
The number of new ASIC design starts is declining, but the revenue per design is rising, according to market research firm Gartner. Recent results from a design start survey revealed the following:

Application-specific standard product (ASSP) design starts gained share over ASIC design starts in 2011 and will continue to gain share in 2012, indicating the growing trend among system companies to shift from using ASICs to ASSPs to avoid the high costs of designing custom chips.

ASIC designs that are 45 nm or less accounted for only 13 percent of total 2011 design starts, but these leading-edge designs will account for greater than 50 percent of revenue in a few years.

Of the total ASIC design starts, nearly 41 percent are estimated to generate less than or about $2 million in revenue, about 29 percent utilized less than or about a million gates, and only about 32 percent are estimated to have a production quantity of over a million units during the life of those designs.

There is still be a large market for 90 nm and 65 nm nodes, as they will account for nearly 39 percent of all chip design starts. Design starts using process nodes less than 45 nm are growing and will account for nearly 40 percent of the market by 2016.

The share of chip designs targeting consumer and data processing segment is estimated to grow marginally, the share of chip designs targeting the communications segment is expected to decline through 2016.

In 2012, Asia/Pacific's share of ASIC and ASSP design starts is estimated to reach 34 percent and 41 percent, respectively. The declining cost of lagging-edge node designs and the growing number of ASIC and ASSP vendors operating, especially out of China, are contributing to this trend.

The Gartner report prescribed three strategies for maximizing design starts: Suppliers should invest in deeper relationships with existing and new partners to form a strong ecosystem in which design reuse can flourish — if not, they will face severe design cost escalation challenges.

Designers should also continue to evaluate all the design options at each process node for