HAPS-80 enterprise configurations support up to 1.6 billion ASIC gates based on the Xilinx Virtex UltraScale FPGA and enable remote usage and multi-design mode for concurrent design execution. Built-in debug capabilities are automatically inserted for greater debugging efficiency and visibility, enabling the capture of thousands of RTL signals. Unified Compile with VCS simulation and Unified Debug with Verdi debug, part of Synopsys’ Verification Continuum platform, eases migration between simulation, emulation and prototyping.
HAPS-80 systems deliver up to 100 MHz multi-FPGA performance and new proprietary high-speed time-domain multiplexing (HSTDM) technology. HAPS-80 with ProtoCompiler design automation and debug software uses the latest Xilinx Virtex UltraScale VU440 devices with 26-million-ASIC-gates capacity per FPGA, and supports designs up to 1.6 billion ASIC gates.
ProtoCompiler software, which has built-in knowledge of the HAPS system architecture, automates partitioning (of a complete SoC design on to several FPGAs; Synopsys claims an average time to first prototype of less than two weeks, and subsequent compile iterations in hours - compared to non-integrated prototypes. ProtoCompiler takes advantage of HAPS-80’s new HSTDM capabilities to automatically select the optimum mix of pin-multiplexing schemes to best match the design under test. The integrated HAPS-80 solution delivers performance of up to 300 MHz for single FPGA designs, up to 100 MHz for multi-FPGA without pin-multiplexing and up to 30 MHz for multi-FPGA with high-speed pin-multiplexing. The increased system performance of the HAPS-80 systems enables OS booting to the command prompt in less than a minute, allowing designers to probe and initialise device hardware such as CPU, timers and UARTs. HAPS-80 also enables at-speed operation of real world I/O.
ProtoCompiler’s automated RTL-to-FPGA image timing-driven flow ... enables the creation of prototypes with an optimum multi-FPGA design partition, lowest pin multiplexing ratios, optimised synthesis and guided FPGA place and route, Synopsys asserts. These features enable designers to use the entire capacity range of HAPS-80, which supports up to 1.6 billion ASIC gates. ProtoCompiler’s hierarchical IP-to-SoC flow encapsulates RTL, design prototyping constraints, pre-defined debug visibility access points and synthesis directives, eliminating the need to replicate these tasks in an SoC.
HAPS-80 systems deliver debug visibility and automation through HAPS Deep Trace Debug Gen4 (DTD4) technology, providing the ability to capture more than 1000 debug signal bits per FPGA at speed. Debug data acquisition, debug storage memory and dedicated debug routes are built into the HAPS-80 systems and automatically inserted by ProtoCompiler to ensure minimally-invasive debug is always available to the user. HAPS DTD4, in combination with Synopsys Verdi debug software, helps designers visualise complex design behaviour in the context of the original RTL source for a simulator-like experience, cutting debug time by as much as half. Integration of HAPS and ProtoCompiler with the Verification Continuum’s Unified Compile technology aids migration between Synopsys VCS simulation, ZeBu emulation and HAPS prototyping.