FPGA control-plane designs for next-generation wireless infrastructure

November 06, 2013 // By Graham Prophet
Lattice Semiconductor has a collaboration with Azcom Technology to further development of HetNet equipment being deployed in response to explosive growth in mobile traffic

The offering is of programmable solutions for building smart, low-power cellular equipment needed to support the global rollout of Heterogeneous Networks (HetNet). In collaboration with Azcom Technology, the Lattice HetNet Solutions Portfolio enables system designers to implement designs for connectivity, control path and power management while accelerating their development with system-level reference designs for multi-mode LTE small cells.

Service providers around the world are deploying a mosaic of wireless equipment in both indoor and outdoor environments including office buildings, public facilities and underground areas to support the explosive growth in mobile data traffic. According to the Small Cell Forum* in a report released at this year’s Mobile World Congress, the small cell market alone is expected to generate $22 billion by 2016.

Lattice claims its HetNet Solutions Portfolio enables designers of small cells, low-power remote radio heads, distributed antenna systems, and active antennas, to achieve the lowest BOM, power consumption and smallest footprint for the connectivity, control path and power management functions of their systems, complementing the ASICs and SOCs used for complex data path functions.

Including soft IP for connectivity, control path and data path functions optimised for low complexity HetNet applications, specific elements of the HetNet Solutions Portfolio include:

Azcom ngSCBP baseband board: 3GPP Release 9 compliant dual mode LTE/HSPA+ small cell baseband platform, with on board Lattice ECP3-70 FPGA implementing CPRI interface management, GPS interface control, glue logic etc.

Azcom ngSCBP- RF board: Simultaneous support for LTE and HSPA+ from 700 MHz to 2.6 GHz, up to 4x4 MIMO and 27 dBm output power, with on board LatticeECP3-150 FPGA implementing digital front end (DFE) functions such as CPRI, multicarrier DUC/DDC, CFR, NCO and JESD207.

Low density LatticeECP3 FPGAs: With up to 16 3.2 Gbps SERDES channels, LatticeECP3 FPGAs offer low cost connectivity solution for implementing interface protocols such as CPRI, JESD204B, SRIO, PCI Express, Ethernet and others.

Ultra low density MachXO2 and new MachXO3 families: form an