FPGA family offers lowest cost per I/O programmable bridging and I/O expansion

September 25, 2013 // By Graham Prophet
Lattice's MachXO3 FPGA family has 640 to 22K logic cells, lowest power, $.01 per I/O cost, and hard IP blocks to ease implementation of emerging connectivity interfaces

Lattice Semiconductor's ultra-low density MachXO3 Field Programmable Gate Array (FPGA) family is a small, lowest-cost-per I/O programmable platform aimed at expanding system capabilities and bridging emerging connectivity interfaces using both parallel and serial I/O. By matching advanced, small-footprint packaging with on-chip resources, the MachXO3 family simplifies the implementation of emerging connectivity interfaces such as MIPI, PCIe, and GbE.

The ultra-low density MachXO3 FPGA family gives customers a single programmable bridge that lets them build differentiated systems using the latest components and interface standards. With advanced package technology solutions that eliminate bond wires to enable lowest-cost and increased I/O density in a small footprint, the MachXO3 family can be used across market segments, including consumer, communications, compute, storage, industrial and automotive.

“The MachXO3 family allows designers to address the disparity among the components within their systems with minimal impact on cost, footprint, and power consumption,” said Brent Przybus, Sr. Director, Product and Corporate Marketing. “As system performance and complexity increases, I/O interfaces often become the bottleneck. Designers want to use the most advanced components, but have to deal with any number of interface standards, many of which are still evolving or are new to many designers, such as MIPI.”

In a low power architecture built on 40nm process technology to deliver lower cost with increased performance for power sensitive applications, the new MachXO3 family delivers a new set of capabilities that enable system engineers to do more in a smaller footprint.

The 640-to-22K logic-cell family makes use of the latest in package technology to not only deliver tiny 2.5 x 2.5 mm wafer-level chip-scale packaging, but also 540 I/O count devices, as well as devices with 3.125 Gbps SERDES capabilities to cover the full spectrum of bridging and interface requirements in consumer, industrial, communications, automotive, and compute markets.

Features include;

- Lowest static and dynamic power consumption for consumer, industrial, and automotive systems where µW static and mW active power