FPGA IP to embed in SoCs for function acceleration

October 12, 2016 // By Graham Prophet
Over time, a number of efforts have been made to integrate a block of programmable logic into an otherwise fully-diffused system-on-chip integrated circuit, with limited success. Now, Achronix Semiconductor says it has resolved the issues preventing the concept being applied.

Where the intention has been (for example) to provide for late design changes, a barrier that has frequently been cited as holding back the concept is the disparity in density between FPGA structures and fully-diffused cells and blocks. Put simplistically, if you lay down enough FPGA to be useful, you use a disproportionate amount of silicon area. (The converse, embedding specific blocks of diffused IP, such as processors cores – e.g. Xilinx Zynq – has been much more successful.)


Now, Achronix (Santa Clara, California) has announced its Speedcore embedded FPGA (eFPGA) IP for integration into designer’s SoCs. Speedcore is designed for compute and network acceleration applications and is based on the same architecture that is in Achronix’s Speedster22i FPGAs that have been shipping in production since 2013.


With Speedcore, designers specify the optimal die size, power consumption and resource configuration required for their end application. They define the quantity of look-up-tables (LUTs), embedded memory blocks and DSP blocks. Additionally, designers define the Speedcore aspect ratio, IO port connections and can make tradeoffs between power and performance. Achronix delivers a GDS II of the Speedcore IP that engineeers integrate directly into their SoC, and a custom, full-featured version of the ACE design tools that customers use to design, verify and program the functionality of the Speedcore eFPGA. Speedcore eFPGA products are fully supported by Achronix’s robust and proven ACE design tools.


“Over the years, different companies have talked about eFPGA products, but Achronix Speedcore is the first eFPGA IP to ship to end customers, and it is a game changer” said Robert Blake, President and CEO, Achronix Semiconductor. “Achronix was the first company to deliver high density FPGAs with embedded system level IP. We are using that same proven methodology to deliver our eFPGA technology to customers who want to combine all the efficiencies of ASIC design with the flexibility of eFPGA programmable hardware accelerators on the same