FPGAs add SERDES and I/O options

February 12, 2016 // By Graham Prophet
Lattice Semiconductor has added to its ECP5 FPGA family aimed at “smart connectivity”-based designs. The range will now support 5G SERDES and up to 85K LUTs in a 10 x 10 mm package, aimed as cost-effectively providing programmable IO bridging functionality in a 12K LUT device.

These additions are pin compatible with ECP5 FPGAs and enable OEMs to update their designs to meet evolving interface requirements in the industrial, communications and consumer markets.

Lattice’s ECP5-5G family supports 5G SERDES and up to 85K LUTs in a 10 x 10 mm package. The ECP5-5G devices support multiple 5G protocols including PCI Express Gen 2.0, CPRI, and JESD204B. This product family enables connectivity to ASICs and ASSPs in a wide array of applications including cameras, displays, gaming platforms, small cells and low-end routers.

ECP5 12K devices offer programmable IO support for popular interface bridging functions including LVDS, MIPI and LPDDR3. The device provides a mix of logic, memory and DSP resources for additional pre and post processing in a variety of applications such as LED controllers, machine vision, and motor control.

Lattice Semiconductor; www.latticesemi.com