FPGAs aim low-power/small outline/mid-density logic mix at interfacing functions

July 22, 2014 // By Graham Prophet
Lattice Semiconductor has announced sampling of the largest member of its recently-released ECP5 programmable logic family. The FPGA family is targeted at high-volume small-cell, microserver, broadband access and video applications and the company claims early design-ins are in areas such as “critical bridging and interface functions”.

The LFE5UM-85 is now available along with the Diamond design tool, development boards, soft IP library, reference designs and hardware demonstrations. Lattice positions its ECP5 FPGAs in a design space where they can offer twice the functional density of competing devices, in a 10 x 10 mm package, at 40% less cost and using 30% less power compared to other options. Their characteristics suit them to programmable connectivity solutions to complement ASICs and ASSPs, Lattice says.

The 85K LUT (look up table) LFE5UM-85 devices sampling now, are the largest in the family and available in the same packages as smaller devices in the family – which enables designers to prototype in the largest device size for convenience and flexibility, then optimise for cost in a lower density device when they go to production. The ECP5 hardware development boards based on the LFE5UM-85 will be available by the end of July 2014.

The company claims initial design interest from over 100 early access customers is typically in critical bridging and interface functions including LPDDR3, PCI Express, MIPI, Ethernet, and USB3.0.

The graphic, above, depicts “smart ball depopulation” of the devices' packages, to simplify routing in high-volume applications.

Lattice Semiconductor; www.latticesemi.com/ecp5