Silicon Labs’ clock jitter tool is the first standardised jitter calculator readily available for the PCIe 1.0, 2.0, 3.0 and 4.0 specifications, at no charge, to anyone developing applications based on the popular PCIe architecture. Designed to support PCIe common clock and separate clock architectures, the tool is open to the industry and not restricted for use with Silicon Labs’ clock products (for example, http://www.silabs.com/products/timing/clock-generator/si521xx/pages/si521xx.aspx).
Silicon Labs’ jitter measurement tool for PCIe technology is available to developers now and can be downloaded free of charge at http://www.silabs.com/pcie-learningcenter
Since its inception as a serial interconnect for desktop PCs more than a decade ago, the PCIe standard has evolved over three generations to become widely deployed in blade servers, storage, embedded computing, IP gateways, industrial systems and consumer electronics. PCIe technology has also been adopted for FPGA and SoC devices to provide a versatile, high-performance means of transferring data within systems. While the PCIe specification specifies a 100 MHz reference clock with ±300 ppm frequency stability, some FPGA and SoC designs may operate internally up to 250 MHz, making clock jitter evaluation a critical design consideration.
Filter masks and jitter calculations for PCIe technology are often misunderstood during the development process. Most oscilloscopes are not equipped with the necessary filter masks to enable correct PCIe clock jitter measurements, which can lead to confusion regarding why a measured result does not match data sheet specifications. Developers often report PCIe jitter measurements higher than clock data sheet specifications, indicating incorrect measurements rather than design issues. As a supplier of PCIe clock products, Silicon Labs created the PCIe jitter tool to address these needs, providing hardware designers with a downloadable utility that quickly determines if the measured clock meets PCIe jitter requirements.