The Layerscape architecture is a fundamental new approach to networking system architectures and includes a family of multicore ARM Cortex (above) and Power Architecture devices.
The architecture modularizes packet acceleration and forwarding operations from high-level routing decisions; streamlines interaction between the layers; leverages a synchronous run-to-completion model; and supports a consistent programming framework across the architecture using standard C/C++ languages. The extreme programming flexibility and scale of the architecture enable real-time, ‘soft’ control over the network, preserve software investments and help to ensure continued evolution.
“To address the need for more intelligent, dynamic networks, Freescale has taken our QorIQ platform a significant step further with the new software-aware Layerscape architecture,” said Tom Deitrich, senior vice president and general manager of Freescale’s Networking & Multimedia Solutions Group. “We’ve made software awareness an integral part of our new architecture instead of an afterthought. With innovations including core-agnostic compatibility, independent, highly efficient packet processing and real-time visualization capability, we’re accelerating the network’s IQ.”
The architecture is the foundation of a broad array of forthcoming QorIQ multicore processors, from many-core data path devices delivering up to 100 Gbps of performance to highly integrated, cost- and energy-efficient products operating at less than 3 W, using both Power Architecture and ARM technologies as appropriate.
The modular Layerscape architecture consists of three independent, scalable layers, allowing Freescale to design QorIQ devices with expanded, reduced or removed layers as needed, providing the optimal solution for a given application. The first of three layers is a General-Purpose Processing Layer (GPPL) for general purpose compute performance. This layer is optimized for virtualized cloud services and control plane applications. The Accelerated Packet Processing Layer (APPL) performs autonomous packet processing and enables customers to program value-added capabilities in a sequential, synchronous, run-to-completion model that abstracts the hardware microarchitecture and gives customers an embedded, C-based programming model. The third, Express Packet I/O Layer (EPIL), provides deterministic wire-rate performance between network interfaces up to