Based on Grenoble's pioneering ecosystem, the IRT partners aim to conduct world-class R&D, and to share their research with all industrial sectors, especially small, medium and intermediate sized enterprises, as well as to provide training in the necessary skills in these areas, specifically micro and nano-electronics. The technological R&D activities will focus on 3D IC integration and integrated silicon-photonics in which manufacturers STMicroelectronics and Mentor Graphics are the most involved. Very advanced technological research using state-of-the-art equipment will undertake by bringing the best possible experts from manufacturers and public laboratories into close partnership.
“I am delighted of the collaboration with Mentor Graphics, whose expertise in computer-aided design (CAD) tools will be able to make CEA-Leti and STMicroelectronics’s advanced technological achievements better available to systems and applications designers,” said Laurent Malier, CEO of CEA-Leti.
The NanoElec IRT is supported by CEA-Leti in partnership with manufacturers such as STMicroelectronics, Mentor Graphics, Soitec, Schneider, STEricsson, Bouygues, Presto Engineering and INEO, the Minalogic international competitive cluster, the Grenoble INP Institute of Technology teaching and research school, the Grenoble Ecole de Management school, the Joseph Fourier university, the INRIA (National Institute for Research in Computer Science and Control), the CNRS (National Center for Scientific Research), the Laue Langevin Institute, and the ESRF (European Synchrotron Radiation Facility).
The semiconductor industry has followed a path defined by Moore’s Law for 40 years. But today, transistor miniaturization is no longer enough to improve performances and reduce consumption. The concept of equivalent scaling and other changes to maintain that rate of progress have been defined as “More than Moore”. The most important of these is 3D IC integration.
The 3D IC integration concept aims to increase performance by stacking components. This additional approach combines with miniaturization to increase semiconductor performance and, at the same time, reduce costs and delays in accessing the market. This new and very different approach requires a large number of major innovations in design, modeling,